1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus, drive method thereof, and an image pickup system. In particular, the present invention relates to an amplification type solid-state image pickup-apparatus having a pixel configuration in which a single amplification transistor receives signals from a plurality of photodiodes, and drive method thereof.
2. Related Background Art
Conventionally, CCDs have been used in many cases as solid-state image pickup apparatuses because of their high signal-to-noise ratio. On the other hand, however, development of so-called amplification type solid-state image pickup apparatus having the advantage of simple usage and low power consumption has been conducted.
The amplification type solid-state image pickup apparatus is a type in which signal charges stored in light receiving pixels are led to a control electrode of a transistor arranged in a pixel section and an amplified signal is output from its main electrode. As for the amplification transistor, there are an SIT image sensor using SITs (static induction transistors) (see, for example, A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,” IEEE trans., June 1986, Vol. ED-33, pp. 735-742), a BASIS using bipolar transistors (see, for example, N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, May 1990, vol. 35, pp. 646-652), a CMD using JFETs (Junction-type field effect transistors) a control electrode of each of which is depleted (see, for example, Nakamura etc., “Gate accumulation type MOS phototransistor image sensor,” Proceedings of the Institute of Television Engineers of Japan, November 1987, Vol. 41, No. 11, pp. 1075-1082), a CMOS sensor using MOS transistors (see, for example, S. K. Mendis, S. E. Kemeny and E. R. Fossum, “A 128×128 CMOS active image sensor for highly integrated imaging systems,” in IEDM Tech. Dig., 1993, pp. 583-586). In particular, CMOS sensors has technological advantages that they match with the CMOS process and is favorable for fabricating a peripheral CMOS circuit on the chip, and consequently great effort has been made in development of the CMOS sensors.
A problem common to these amplification type solid-state image pickup apparatuses is that the output offset of an amplification transistor for each pixel differs from pixel to pixel and consequently fixed pattern noise (FPN) is added to an image sensor signal. In order to remove this FPN, various signal readout circuits have been devised heretofore. Furthermore, CMOS sensors have a drawback that the number of MOS transistors forming one pixel is larger and pixel contraction is difficult as compared with CCDs.
On the other hand, a CMOS sensor having a configuration in which one common amplifier is provided for a plurality of pixels was proposed (see, for example, Japanese Patent Application Laid-Open Publication No. 2000-78474). In this CMOS sensor, pixel contraction is facilitated because of the reduction of the number of MOS transistors in a pixel.
FIG. 5 is a circuit diagram showing a common amplifier type CMOS image sensor. In order to simplify the description, it is supposed in FIG. 5 that a pixel section has a pixel configuration of two rows (horizontal direction) by two columns (vertical direction) and pixels corresponding to two rows adjacent form a pixel unit serving as one unit cell.
In the common amplifier type CMOS image sensor shown in FIG. 5, reference numeral 1 denotes a pixel unit formed of two pixels included in the pixel section, and 2-1 and 2-2 denote photodiodes in two rows (first and second rows) for receiving light and storing signal charge in the pixel unit 1. Reference numeral 3 denotes an amplification MOS transistor for amplifying the signal charge accumulated in the photodiode 2-1 or 2-2 and outputting the amplified signal charge. Reference numerals 4-1 and 4-2 denote transfer MOS transistors respectively for transferring the signal charge accumulated in the photodiodes 2-1 and 2-2 to a gate electrode section in the amplification MOS transistor 3. Reference numeral 5 denotes a reset MOS transistor for resetting a gate electrode potential of the amplification MOS transistor 3. Reference numeral 6 denotes an electric power supply voltage supply line. Drain electrodes of the reset MOS transistor 5 and the amplification MOS transistor 3 are connected in common to the electric supply voltage supply line.
Reference numeral 7 denotes a selection switch MOS transistor for selecting the amplification MOS transistor 3. Reference numeral 8 denotes a pixel output line (vertical output line). When the selection switch MOS transistor 7 turns on, then transmission between a source electrode of the amplification MOS transistor 3 and the pixel output line 8 is attained, and a signal output of a selected amplification MOS transistor 3 is led to the pixel output line 8.
Reference numeral 9 denotes a constant current supply MOS transistor for supplying a constant current to the pixel output line 8. The selected amplification MOS transistor 3 is activated to operate as a source follower via the selection switch MOS transistor 7. Thus, a potential having a certain voltage difference with respect to the gate potential of the amplification MOS transistor 3 appears on the pixel output line 8.
Reference numerals 10-1 and 10-2 denote transfer control lines (horizontal drive lines) for controlling the gate potentials of the transfer MOS transistors 4-1 and 4-2, respectively. Reference numeral 11 denotes a reset control line (horizontal drive line) for controlling the gate potential of the reset MOS transistor 5. Reference numeral 12 denotes a selection control line for controlling the gate potential of the selection MOS transistor 7. Reference numeral 13 denotes a constant potential supply line for supplying a constant potential to the gate of the constant current supply MOS transistor 9 so as to make the constant current supply MOS transistor 9 operate in a saturate region to function as a constant current supply.
Reference numerals 14-1 and 14-2 denote drive pulse terminals for supplying a transfer pulse to the transfer control lines 10-1 and 10-2, respectively. Reference numeral 15 denotes a drive pulse terminal for supplying a reset pulse to the reset control line 11. Reference numeral 16 denotes a drive pulse terminal for supplying a selection pulse to the selection control line 12. Reference numeral 17 denotes a vertical scanning circuit for successively selecting and scanning rows of pixels arranged in a matrix form. Reference numeral 18 denotes an output line of the vertical scanning circuit 17.
Reference numerals 19-1 and 19-2 denote switch MOS transistors for leading pulses from the drive pulse terminals 14-1 and 14-2 to the transfer control lines 10-1 and 10-2, respectively. Reference numeral 20 denotes a switch MOS transistor for leading a pulse from the drive pulse terminal 15 to the reset control line 11. Reference numeral 21 denotes a switch MOS transistor for leading a pulse from the drive pulse terminal 16 to the selection control line 12. Gates of these switch MOS transistors 19-1, 19-2, 20 and 21 are connected to the row selection output line 18. A line in which pixels are driven is determined depending on a state of the row selection output line 18.
Reference numeral 22 denotes a readout circuit for reading out outputs from a pixel. Reference numeral 23 denotes a capacitance (storage capacitance) for holding a reset level output of a pixel. Reference numeral 24 denotes a capacitance (storage capacitance) for holding photo-signal output of a pixel. Reference numeral 25 denotes a switch MOS transistor between the pixel output line 8 and the capacitance 23. Reference numeral 26 denotes a switch MOS transistor between the pixel output line 8 and the capacitance 24. Reference numeral 27 denotes a noise output line (horizontal output line) to which a reset output held in the capacitance 23 is led. Reference numeral 28 denotes a signal output line (horizontal output line) to which a photosignal output held in the capacitance 24 is led. Reference numeral 29 denotes a switch MOS transistor between the capacitance 23 and the noise output line 27. Reference numeral 30 denotes a switch MOS between the capacitance 24 and the signal output line 28. Reference numeral 31 denotes a noise output line reset MOS transistor for resetting a potential on the noise output line 27. Reference numeral 32 denotes a signal output line reset MOS transistor for resetting a potential on the signal output line 28. Reference numeral 33 denotes a reset power supply terminal for supplying a reset potential to source electrodes of the noise output line reset MOS transistor 31 and the signal output line reset MOS transistor 32. Reference numeral 34 denotes a horizontal scanning circuit for successively selecting a pair of the capacitances provided for every column of pixels arranged in the matrix form. Reference numeral 35-1 denotes an output line for selecting a first column, and 35-2 denotes an output line for selecting a second column. Two output lines 35-1 and 35-2 of the horizontal scanning circuit 34 are connected to corresponding switch MOS transistors 29 and 30 respectively.
Reference numeral 36 denotes a pulse supply terminal for applying a pulse to gates of the reset MOS transistors 31 and 32. Reference numerals 37 and 38 denote pulse supply terminals for applying a pulse to gates of the switch MOS transistors 25 and 26, respectively. Reference numeral 39 denotes a differential amplifier for taking a difference voltage between the potential on the noise output line 27 and the potential on the signal output line 28 and outputting the amplified difference voltage. Reference numeral 40 denotes an output terminal of the differential amplifier 39.
Operation conducted by the common amplifier type CMOS image sensor shown in FIG. 5 will now be described with reference to a timing chart shown in FIG. 6. It is now supposed that all MOS transistors shown in FIG. 5 are N type and each of the MOS transistors is in its on-state when its gate potential is at a high level whereas each of the MOS transistors is in its off-state when its gate potential is at a low level. Numbers indicating timing pulses in FIG. 6 (φ14-1, φ14-2, φ15, φ16, φ18, φ35-1, φ35-2, φ36, φ37 and φ38) correspond with the drive pulse input terminals 14-1, 14-2, 15, 16, the output line 18 of the vertical scanning circuit 17, the output lines 35-1 and 35-2 of the horizontal scanning circuit 34, and the drive pulse input terminals 36, 37 and 38 shown in FIG. 5.
First, when the drive pulse φ18 output to the output line 18 of the vertical scanning circuit 17 is changed to the high level by operation of the vertical scanning circuit 17, then it becomes possible for the pixel section shown in FIG. 5 to operate. When in this state the drive pulse φ16 input to the terminal 16 becomes the high level, then the source of the amplification MOS transistor 3 of the pixel is connected to the constant current supply MOS transistor 9 serving as the constant current supply source via the output line 8 and thereby the source follower output of the pixel is output to the output line 8.
By shifting the drive pulse φ15 input to the terminal 15 to its high level, the gate section of the amplification MOS transistor 3 is reset by the reset MOS transistor 5. In case that subsequently the drive pulse φ37 at the high level is applied to the terminal 37, then a reset level output of the amplification MOS transistor 3 is stored in the capacitance 23 via the MOS transistor 25.
Subsequently, by applying the drive pulse φ14-1 of the high level to the terminal 14-1, the signal charge stored in the photodiode 2-1 in the first row is transferred to the gate of the amplification MOS transistor 3 via the transfer MOS transistor 4-1 in the first row. When subsequently the drive pulse φ38 at the high level is applied to the terminal 38, a signal output superimposed on the reset level is stored in the capacitance 24 via the switch MOS transistor 26. Variance appears on the reset output of pixels because there are variance in threshold voltages of the amplification MOS transistors 3 for pixels.
Therefore, a difference between outputs stored in the capacitance 23 and in the capacitance 24 is a pure signal free from noise. Then, when the horizontal scanning circuit 34 is activated, therefore, the drive pulses φ35-1 and φ35-2 respectively output to its output lines 35-1 and 35-2 successively shift to the high level, and outputs stored in the capacitances 23 and 24 in each column are led to the horizontal output lines 27 and 28 via the MOS transistors 29 and 30, respectively. Before the drive pulses φ35-1 and φ35-2 of the high level respectively at the terminals 35-1 and 35-1 are output, it is necessary to shift the drive pulse φ36 to the high level and reset the horizontal output lines 27 and 28 via the MOS transistors 31 and 32.
The pixel reset level output and the signal output plus the pixel reset level output led respectively to the horizontal output lines 27 and 28 are input to the differential amplifier 39. The signal output from which the reset level is subtract, i.e., the pixel signal free from noise is output from the output terminal 40. Outputting the signal charge stored in the photo-diode 2-2 in the second row is accomplished by applying the drive pulse φ14-2 to the terminal 14-2 instead of the terminal 14-1 and conducting other drives in the same way as outputting of the signal charge stored in the photodiode 2-1 in the first row.
In the configuration and operation described heretofore, pixels are read row by row. On the other hand, the technique of reading out every two rows in order to shorten the readout time of the whole frame is also known.
FIG. 7 is a circuit diagram showing a solid-state image pickup apparatus corresponding to such a case. FIG. 7 shows a pixel unit and two readout circuit systems connected to a pixel output line of the pixel unit. In FIG. 7, components forming each of the readout circuit systems are the same as those shown in FIG. 5. Each of components is denoted with a suffix 1 or 2 so as to be associated with one of the two readout circuit systems. For simplicity, only one column is shown in FIG. 7, and description of the vertical scanning circuit and pixel unit is omitted. These omitted components are the same as those of FIG. 5.
In the solid-state image pickup apparatus shown in FIG. 7, readout from the pixel can be implemented by storing the reset level output of the amplification MOS transistor 3 and a signal corresponding to the photodiode 2-1 in the first row, in one readout circuit 22-1 and subsequently storing the reset level output of the amplification MOS transistor 3 and a signal corresponding to the photodiode 2-2 in the second row, in the other readout circuit 22-2. Subsequently, horizontal scanning is conducted. In this horizontal scanning, two readout circuits 22-1 and 22-2 are simultaneously driven. As a result, pixel signals corresponding to the two rows are output in parallel at the same time.
As heretofore described, in the CMOS sensor including the amplification transistor common to a plurality of photodiodes, pixel contraction is possible and, in addition, a signal having a high signal-to-noise ratio can be output.
In the conventional art in which consecutive readout from two rows shown in FIG. 7 is conducted, however, time required for readout from pixels to the readout circuit is twice the time required for readout from pixels of to one row. The readout from the pixels to the readout circuit is conducted within a horizontal blanking period. Especially in image sensors for moving pictures, the horizontal blanking period is limited by standards. In the case where the pixel readout time corresponding to two rows exceeds the horizontal blanking time, the two-row readout method cannot be used, resulting in a drawback.